Along with size reduction achieved by the semiconductor technology, an error rate of the errors occurring in a cache RAM (random access memory) has been increasing. A RAM has a plurality or bit lines extending in a vertical direction and a plurality of word lines extending in a horizontal direction, and a one-bit memory cell is disposed at each intersection of these lines. In order to read data from the RAM, a word line address (i.e., word address) and a bit line address (i.e., column address) are specified to read data located at the specified intersection.
As a result of reduction in the distance between word lines due to reduction in the size of semiconductor devices, a word line failure is more likely to occur in RAMs due to short-circuiting or the like. With the occurrence of a word line failure, access to all the memory cells that are read and written by this word line results in an error. For example, a 4-column cache RAM may be configured such that one access address in the RAM corresponds to one cache line. In this case, four access addresses in the RAM that correspond to the same word line and different column addresses share one word line, so that four cache lines share one word line. When such a cache RAM suffers a word line failure, access results in an error with respect to all the bits associated with the four access addresses sharing the failed word line in the RAM. In this case, the four cache lines corresponding to these four access addresses in the RAM are not usable.
Several technologies are known as a method of recovering from a cache RAM error. A cache control unit may be provided with a plurality of operation bits which are assigned to respective lines in the cache memory (Paten Document 1, for example). These operation bits indicate whether the cache memory is properly operating, and are set to “valid” in the case of the normal operation state. Upon an error being detected, an operation bit assigned to the failed line is set to “invalid”. At the time of accessing the cache, a check is made whether all the operation bits of the line to which the data to be accessed belongs indicate “valid”. When the operation bits indicate “valid”, the cache memory is accessed. When the operation bits indicate “invalid”, an external memory, rather than the cache memory, is accessed.
In another example, a monitoring register may be provided to store a cache line address and a cache way that have failed (Patent Document 2, for example). Upon detecting a failure, the monitoring register stores the failed address and failed way, and, also, the relevant cache line is disabled. At the time of accessing a cache memory, the cache line address that is to be accessed is compared with the cache line address stored in the monitoring register. A match between these addresses indicates that the failed cache line is to be accessed. When the failed cache line is to be accessed, device control (i.e., block delete) is performed to store data in a way that is different from the failed way indicated by the monitoring register. With respect to the way stored in the monitoring register, another cache line may fail. In such a case, the entirety of the way is made obsolete (i.e., way-delete), and operations continue by use of the remaining ways.
In the configuration, disclosed in Patent Document 1, cache lines may be made obsolete on a line-specific basis, so that recovery can be made from a word line failure. However, operation bits are provided for respective cache lines, which results in an increase in circuit size.
In the configuration disclosed in Patent Document 2, the block delete can provide recovery from a failure of a single cache line. The block delete cannot provide recovery from a word line failure in which a plurality of cache lines fail at the same time. Further, the way delete can provide recovery from a word line failure. Since an excessively large area (i.e., the entirety of one way) is made obsolete, however, a significant drop in performance may needlessly occur.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2011-8491    [Patent Document 2] Japanese Patent No. 4392049